Wafer fabrication methods and apparatus that use such techniques as vacuum deposition to form semiconductor-based devices of various kinds are well known. Such techniques serve well for many purposes and can achieve high reliability, small size, and relative economy when applied in high volume settings. Recently, other techniques are being explored to yield semiconductor-based devices. For example, organic or inorganic semiconductor materials can be provided as a functional ink and used in conjunction with various printing techniques to yield printed semiconductor devices.
Printed semiconductor devices, however, yield considerably different end results and make use of considerably different fabrication techniques than those skilled in the art of traditional semiconductor manufacturing are prone to expect. For example, printed semiconductor devices tend to be considerably larger than typical semiconductor devices that are fabricated using more traditional techniques. As other examples, both the materials employed and the deposition techniques utilized are also well outside the norm of prior art expectations.
Due in part to such differences, semiconductor device printing gives rise to challenges and difficulties that are without parallel in prior art practice. As one example, printed transistors (such as field effect transistors) are typically formed by printing successive layers of inks on top of one another to form the completed device. Each layer is typically defined by a plate, screen, or other patterning technique known in the printing industry. In general, these successive layers align with one another, but typically only within some corresponding tolerance. The printing industry sometimes refers to such layer alignment tolerance as layer-to-layer registration. The printing industry typically accommodates such registration issues by ensuring overlap between such layers.
In the case of a transistor channel, the channel typically needs to be aligned over a gate electrode such that no part of the channel resides unaligned with the gate electrode. Traditional silicon wafer fabrication techniques often employ a self-aligning gate technique to effectively reduce such non-alignment to zero. Masks are used to effect this technique, however, and thus are not useful in a printing context. To meet this requirement, typical printing techniques would suggest increasing the size of the gate region to ensure such a result consistent with expected registration tolerances. This, however, unfortunately also requires overlap between the gate electrode and the other electrodes of the transistor (such as the drain electrode and the source electrode). And this, in turn, gives rise to undesirable parasitic capacitances that slow down the switching time of the transistor itself.
Unfortunately, various proposed solutions to this problem are not without significant issues themselves. For example, by one approach, one might simply try to improve layer-to-layer registration. Such a solution, however, may be prohibitively costly and or may require presently unachievable modifications of the printing platform itself. As another example, one might seek to reduce the dielectric constant of a dielectric material that separates the gate electrode from the other electrodes. This approach, however, will also tend to reduce the desirable capacitance that one seeks to establish between the gate electrode and the semiconductor channel, thereby reducing current flow and potentially raising operating voltage requirements.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein.